Classical hardware and algorithms that turn the stream of syndrome measurements of an error-correcting code into corrections, fast enough that the quantum computer never waits for them.
Scope
In scope: the decoding algorithm, its implementation on FPGA or ASIC, and its latency and throughput during a live experiment. Out of scope: the choice of code, the qubits themselves (quantum/fault-tolerant-quantum-computer) and the cryogenic electronics it may sit on (enablers/cryogenic-control-electronics).
Decoder latency headline0.8 orders of magnitude to go
Time from the end of a syndrome measurement to the decoder's correction, in real-time decoding. Lower is better.
Current (2024-12-09)6.3 × 10⁻⁵ s
Target10⁻⁵ s
Limit–
Conditions. Average real-time decoder latency in a running experiment: distance-5 surface code, cycle time 1.1 microseconds.
Why this target. The control-system reaction time of 10 microseconds assumed by the RSA-2048 resource estimate (gidney2025how).
Note. Other decoder studies report times per measurement round under modeled noise (liyanage2024fpga); these are not end-to-end latencies in an experiment and are not used as current values.
Cryogenic control electronicsThe decoder reads syndromes from the control system, and placing it near the qubits shortens the path and the latency.
Required by
Fault-tolerant quantum computerEvery error-correction cycle needs its syndromes decoded before the next logical operation that depends on them. Need: Reaction time of 10 microseconds, the figure assumed in the RSA-2048 resource estimate (gidney2025how).